Subelement B: MF-HF-DSC-SITOR (NBDP) Equip. & Operations— Topic :
Question 16B6
Element 9 (GMDSS Maintainer)What is the purpose of a phase comparator in a frequency synthesizer?
Explanation
In a frequency synthesizer, which typically uses a Phase-Locked Loop (PLL) architecture, the phase comparator is a critical component. Its purpose is to compare the phase and frequency of two input signals.
1. **Reference Signal:** One input comes from a highly stable master (reference) oscillator. This signal is often passed through a fixed frequency divider (R-divider) to create a lower, stable reference frequency for the comparator.
2. **Feedback Signal:** The other input comes from the Voltage-Controlled Oscillator (VCO), which produces the synthesizer's output frequency. This VCO output is fed back through a variable frequency divider (N-divider).
The phase comparator then compares these two *divided* signals. If a phase or frequency difference exists, it generates an error voltage. This error voltage, after passing through a loop filter, adjusts the VCO's frequency until the two *divided* inputs to the phase comparator are precisely identical in frequency and phase.
Therefore, the phase comparator compares the *divided output of the master oscillator* with the *divided output of the voltage-controlled oscillator*. This allows the VCO to generate a stable output frequency that is a precise multiple of the (divided) reference frequency, thus "synthesizing" new frequencies.
* **A) Correct:** This describes the standard operation of a PLL frequency synthesizer, where both the reference and the VCO output are divided before comparison.
* **B) Incorrect:** Comparing direct outputs would only lock the VCO to the master oscillator's exact frequency, not synthesize new ones.
* **C) Incorrect:** While possible in some simplified scenarios, it's not the most general or versatile method for synthesizing a wide range of frequencies, as the master oscillator's direct frequency might be too high or limit resolution.
* **D) Incorrect:** This configuration would lead to the VCO locking to a frequency related to the *divided* master, but would not typically allow for the *multiplication* of the reference frequency by the N-divider in the VCO's feedback path to generate higher frequencies.
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