Subelement A: RADAR Principles – 10 Key Topics – 10 Exam Questions – 8 Drawings— Topic 10: Circuits-2
Question 8-10A1
Element 8 (RADAR)In the circuit shown in Fig. 8A4, U5 pins 1 and 4 are high and both are in the reset state. Assume one clock cycle occurs of Clk A followed by one cycle of Clk B. What are the output states of the two D-type flip flops?
Explanation
The circuit shows two D-type flip-flops (FFs), U5-1 and U5-2, which are positive edge-triggered.
1. **D-type Flip-Flop Operation:** A D-type flip-flop latches the logic level present at its D (data) input and transfers it to its Q output on the active (rising) edge of the clock signal.
2. **Reset Inputs (Pins 1 and 4):** These are the active-low clear (CLR) or reset inputs. The problem states they are "high." This means the reset function is inactive, allowing the flip-flops to operate normally and respond to their clock and data inputs. (If they were low, the Q outputs would be forced low, regardless of D or clock.)
3. **Input Data (Pins 2 and 12):** Both D inputs (Pin 2 for FF1 and Pin 12 for FF2) are connected to Vcc, which represents a logic HIGH state.
4. **Clocking Sequence:**
* **Clk A cycle:** The first clock cycle is applied to Clk A (Pin 3), which is the clock input for FF1. On the rising edge of Clk A, FF1 latches its D input (which is HIGH). Therefore, Pin 5 (Q output of FF1) goes HIGH.
* **Clk B cycle:** The second clock cycle is applied to Clk B (Pin 11), the clock input for FF2. On the rising edge of Clk B, FF2 latches its D input (which is also HIGH). Therefore, Pin 9 (Q output of FF2) goes HIGH.
After both clock cycles, both flip-flops have latched a HIGH input to their respective Q outputs. Thus, Pin 5 will be high and Pin 9 will be high.
The final answer is $\boxed{D}$