Question 3-35E3

In positive logic, a high voltage level (like +5V) represents a logic HIGH (binary 1), and a low voltage level (like 0V or ground) represents a logic LOW (binary 0). The circuit in Figure 3E13 consists of three NAND gates. 1. **Gate 1 (NAND):** The inputs to Gate 1 are both connected to +5V, which means both inputs are HIGH. For a NAND gate, if both inputs are HIGH, the output is LOW. Therefore, test point **A is LOW**. 2. **Gate 2 (NAND):** Similarly, the inputs to Gate 2 are both connected to +5V, making both inputs HIGH. As with Gate 1, the output for a NAND gate with two HIGH inputs is LOW. Therefore, test point **B is LOW**. 3. **Gate 3 (NAND):** The inputs to Gate 3 are the outputs of Gate 1 (A) and Gate 2 (B). Since A is LOW and B is LOW, both inputs to Gate 3 are LOW. For a NAND gate, if both inputs are LOW, the output is HIGH. Therefore, test point **C is HIGH**. Based on this analysis, the correct logic levels are A is low, B is low, and C is high. An answer suggesting A, B, and C are all high would contradict the fundamental truth table of a NAND gate, as a NAND gate with both inputs HIGH produces a LOW output, and a NAND gate with both inputs LOW produces a HIGH output.